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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adf4106 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-470 0 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 pll frequency synthesizer features 6.0 ghz bandwidth 2.7 v to 3.3 v power supply separate charge pump supply (v p ) allows extended tuning voltage in 3 v systems programmable dual modulus prescaler 8/9, 16/17, 32/33, 64/65 programmable charge pump currents programmable anti-backlash pulsewidth 3-wire serial interface analog and digital lock detect hardware and software power-down mode applications broadband wireless access instrumentation wireless lans base stations for wireless radio functional block diagram 14-bit r counter r counter latch function latch ab counter latch 24-bit input register 22 14 ref in clk data le av dd dv dd phase frequency detector charge pump reference v p cpgnd r set current setting 2 current setting 1 cpi3 cpi2 cpi1 cpi6 cpi5 cpi4 lock detect cp muxout av dd sd out high z 19 13-bit b counter prescaler p/p + 1 rf in a rf in b 6-bit a counter from function latch load load m3 m2 m1 mux 6 n = bp + a ce agnd dgnd adf4106 13 general description the adf4106 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. it consists of a low-noise digital pfd (phase frequency detector), a precision charge pump, a programmable reference divider, programmable a and b counters and a dual-modulus prescaler (p/p + 1). the a (6-bit) and b (13-bit) counters, in conjunction with the dual modulus prescaler (p/p + 1), implement an n divider (n = bp + a). in addition, the 14-bit reference counter (r counter), allows selectable refin frequencies at the pfd input. a complete pll (phase-locked loop) can be implemented if the synthe- sizer is used with an external loop filter and vco (voltage controlled oscillator). its very high bandwidth means that frequency doublers can be eliminated in many high-frequency systems, simplifying system architecture and lowering cost.
rev. 0 C2C adf4106?pecifications 1 bchips 2 parameter b version 1 (typ) unit test conditions/comments rf characteristics see figure 3 for input circuit rf input frequency (rf in ) 3 0.5/6.0 0.5/6.0 ghz min/max rf input sensitivity C 10/0 C 10/0 dbm min/max maximum allowable prescaler output frequency 4 300 300 mhz max refin characteristics refin input frequency 20/250 20/250 mhz min/max for f < 20 mhz, use dc-coupled square wave, (0 to v dd ) refin input sensitivity 5 0.8/av dd 0.8/av dd v p-p min/max ac-coupled; when dc-coupled, 0 to v dd max (cmos compatible) refin input capacitance 10 10 pf max refin input current 100 100 a max phase detector phase detector frequency 6 56 56 mhz max charge pump i cp sink/source programmable, see table v high value 5 5 ma typ with r set = 5.1 k ? low value 625 625 a typ absolute accuracy 2.5 2.5 % typ with r set = 5.1 k ? r set range 2.7/10 2.7/10 k ? typ see table v i cp three-state leakage current 1 1 na typ sink and source current matching 2 2 % typ 0.5 v v cp v p C 0.5 v i cp vs. v cp 1.5 1.5 % typ 0.5 v v cp v p C 0.5 v i cp vs. temperature 2 2 % typ v cp = v p /2 logic inputs v inh , input high voltage 1.4 1.4 v min v inl , input low voltage 0.6 0.6 v max i inh /i inl , input current 1 1 a max c in , input capacitance 10 10 pf max logic outputs v oh , output high voltage 1.4 1.4 v min open drain output chosen 1 k ? pull-up to 1.8 v v oh , output high voltage 1.4 1.4 v min cmos output chosen i oh 100 100 a max v ol , output low voltage 0.4 0.4 v max i ol = 500 a power supplies av dd 2.7/3.3 2.7/3.3 v min/v max dv dd av dd av dd v p av dd /5.5 av dd /5.5 v min/v max av dd v p 5.5 v i dd 7 (ai dd + di dd ) 15 13 ma max 13 ma typ i p 0.4 0.4 ma max t a = 25 c power-down mode 8 (ai dd + di dd )10 10 a typ (av dd = dv dd = 3 v 10%; av dd v p 5.5 v; agnd = dgnd = cpgnd = 0 v; r set = 5.1 k ; dbm referred to 50 ; t a = t min to t max unless otherwise noted.)
C3C rev. 0 bchips 2 parameter b version 1 (typ) unit test conditions/comments noise characteristics adf4106 phase noise floor 9 C 174 C 174 dbc/hz typ @ 25 khz pfd frequency C 166 C 166 dbc/hz typ @ 200 khz pfd frequency C 159 C 159 dbc/hz typ @ 1 mhz pfd frequency phase noise performance 10 @ vco output 900 mhz output 11 C 93 C 93 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency 5800 mhz output 12 C 74 C 74 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency 5800 mhz output 13 C 84 C 84 dbc/hz typ @ 1 khz offset and 1 mhz pfd frequency spurious signals 900 mhz output 11 C 90/ C 92 C 90/ C 92 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency 5800 mhz output 12 C 65/ C 70 C 65/ C 70 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency 5800 mhz output 13 C 70/ C 75 C 70/ C 75 dbc typ @ 1 mhz/2 mhz and 1 mhz pfd frequency notes 1 operating temperature range (b version) is C 40 c to +85 c. 2 the bchip specifications are given as typical values. 3 use a square wave for lower frequencies, below the mimimum stated. 4 this is the maximum operating frequency of the cmos counters. the prescaler value should be chosen to ensure that the rf input is divided down to a frequency that is less than this value. 5 av dd = dv dd = 3 v 6 guaranteed by design. sample tested to ensure compliance. 7 t a = 25 c; av dd = dv dd = 3 v; p = 16; rf in = 6.0 ghz 8 t a = 25 c; av dd = dv dd = 3.3 v; r = 16383; a = 63; b = 891; p = 32; rf in = 6.0 ghz 9 the synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 20 logn (where n is the n divider value). 10 the phase noise is measured with the eval-adf4106eb1 evaluation board and the hp8562e spectrum analyzer. the spectrum analyzer provides the refin for the synthesizer (f refout = 10 mhz @ 0 dbm). 11 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 900 mhz; n = 4500; loop b/w = 20 khz 12 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 5800 mhz; n = 29000; loop b/w = 20 khz 13 f refin = 10 mhz; f pfd = 1 mhz; offset frequency = 1 khz; f rf = 5800 mhz; n = 5800; loop b/w = 100 khz specifications subject to change without notice. (av dd = dv dd = 3 v 10%; av dd v p 5.5 v; agnd = dgnd = cpgnd = 0 v; r set = 5.1 k ; t a = t min to t max unless otherwise noted.) clock db23 (msb) db22 db2 db1 (control bit c2) t 5 data le db0 (lsb) (control bit c1) t 6 t 1 t 2 t 3 t 4 le figure 1. timing diagram timing characteristics limit at t min to t max parameter (b version) unit test conditions/comments t 1 10 ns min data to clock setup time t 2 10 ns min data to clock hold time t 3 25 ns min clock high duration t 4 25 ns min clock low duration t 5 10 ns min clock to le setup time t 6 20 ns min le pulsewidth guaranteed by design but not production tested. adf4106
rev. 0 adf4106 C4C absolute maximum ratings 1, 2 (t a = 25 c unless otherwise noted.) av dd to gnd 3 . . . . . . . . . . . . . . . . . . . . . . C 0.3 v to +3.6 v av dd to dv dd . . . . . . . . . . . . . . . . . . . . . . C 0.3 v to +0.3 v v p to gnd . . . . . . . . . . . . . . . . . . . . . . . . . C 0.3 v to +5.3 v v p to av dd . . . . . . . . . . . . . . . . . . . . . . . . . C 0.3 v to +5.5 v digital i/o voltage to gnd . . . . . . . . C 0.3 v to v dd + 0.3 v analog i/o voltage to gnd . . . . . . . . . C 0.3 v to v p + 0.3 v ref in , rf in a, rf in b to gnd . . . . . . C 0.3 v to v dd + 0.3 v operating temperature range industrial (b version) . . . . . . . . . . . . . . . C 40 c to +85 c storage temperature range . . . . . . . . . . . . C 65 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . 150 c tssop ja thermal impedance . . . . . . . . . . . . . 150.4 c/w csp ja thermal impedance . . . . . . . . . . . . . . . . . . 122 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 this device is a high-performance rf integrated circuit with an esd rating of <2 kv and it is esd sensitive. proper precautions should be taken for handling and assembly. 3 gnd = agnd = dgnd = 0 v ordering guide model temperature range package option * ADF4106BRU C 40 c to +85 c ru-16 adf4106bcp C 40 c to +85 c cp-20 * ru = thin shrink small outline package (tssop) cp = chip scale package contact the factory for chip availability. note that aluminum bond wire should not be used with the adf4106 die. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adf4106 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. 0 adf4106 C5C pin configurations pin function descriptions mnemonic function r set connecting a resistor between this pin and cpgnd sets the maximum charge pump output current. the nominal voltage potential at the r set pin is 0.6 v. the relationship between i cp and r set is i r cp max set = 25 5 . so, with r set = 5.1 k ? , i cpmax = 5 ma. cp charge pump output. when enabled this provides i cp to the external loop filter, which in turn drives the external vco. cpgnd charge pump ground. this is the ground return path for the charge pump. agnd analog ground. this is the ground return path of the prescaler. rf in b complementary input to the rf prescaler. this point must be decoupled to the ground plane with a small bypass capacitor, typically 100 pf. see figure 3. rf in a input to the rf prescaler. this small signal input is ac coupled to the external vco. av dd analog power supply. this may range from 2.7 v to 3.3 v. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. av dd must be the same value as dv dd . ref in reference input. this is a cmos input with a nominal threshold of v dd /2 and a dc equivalent input resistance of 100 k ?. see figure 2. this input can be driven from a ttl or cmos crystal oscillator or it can be ac coupled. dgnd digital ground ce chip enable. a logic low on this pin powers down the device and puts the charge pump output into three-state mode. taking the pin high will power up the device depending on the status of the power-down bit f2. clk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into the 24-bit shift register on the clk rising edge. this input is a high impedance cmos input. data serial data input. the serial data is loaded msb first with the two lsbs being the control bits. this input is a high impedance cmos input. le load enable, cmos input. when le goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. muxout this multiplexer output allows either the lock detect, the scaled rf or the scaled reference frequency to be accessed externally. dv dd digital power supply. this may range from 2.7 v to 3.3 v. decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. dv dd must be the same value as av dd . v p charge pump power supply. this should be greater than or equal to v dd . in systems where v dd is 3 v, it can be set to 5 v and used to drive a vco with a tuning range of up to 5 v. tssop top view (not to scale) r set cp cpgnd agnd rf in b rf in a av dd ref in v p dv dd muxout le data clk ce dgnd adf4106 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 chip scale package 15 muxout 14 le 13 data 12 clk cpgnd 1 agnd 2 agnd 3 20 cp 11 ce av dd 6 av dd 7 ref in 8 dgnd 9 dgnd 10 rf in b 4 rf in a 5 19 r set 18 v p 17 dv dd 16 dv dd pin 1 indicator top view adf4106 note: transistor count 6425 (cmos), 303 (bipolar)
rev. 0 adf4106 typical performance characteristics C6C freq unit ghz param type s data format ma freq mags11 angs11 3.300 0.42777 102.748 3.400 0.42859 107.167 3.500 0.43365 111.883 3.600 0.43849 117.548 3.700 0.44475 123.856 3.800 0.44800 130.399 3.900 0.45223 136.744 4.000 0.45555 142.766 4.100 0.45313 149.269 4.200 0.45622 154.884 4.300 0.45555 159.680 4.400 0.46108 164.916 4.500 0.45325 168.452 4.600 0.45054 173.462 4.700 0.45200 176.697 4.800 0.45043 178.824 4.900 0.45282 174.947 5.000 0.44287 170.237 5.100 0.44909 166.617 5.200 0.44294 162.786 5.300 0.44558 158.766 5.400 0.45417 153.195 5.500 0.46038 147.721 5.600 0.47128 139.760 5.700 0.47439 132.657 5.800 0.48604 125.782 5.900 0.50637 121.110 6.000 0.52172 115.400 freq mags11 angs11 0.500 0.89148 17.2820 0.600 0.88133 20.6919 0.700 0.87152 24.5386 0.800 0.85855 27.3228 0.900 0.84911 31.0698 1.000 0.83512 34.8623 1.100 0.82374 38.5574 1.200 0.80871 41.9093 1.300 0.79176 45.6990 1.400 0.77205 49.4185 1.500 0.75696 52.8898 1.600 0.74234 56.2923 1.700 0.72239 60.2584 1.800 0.69419 63.1446 1.900 0.67288 65.6464 2.000 0.66227 68.0742 2.100 0.64758 71.3530 2.200 0.62454 75.5658 2.300 0.59466 79.6404 2.400 0.55932 82.8246 2.500 0.52256 85.2795 2.600 0.48754 85.6298 2.700 0.46411 86.1854 2.800 0.45776 86.4997 2.900 0.44859 88.8080 3.000 0.44588 91.9737 3.100 0.43810 95.4087 3.200 0.43269 99.1282 keyword r impedance ?50 tpc 1. s-parameter data for the rf input rf input frequency ghz 0 01 30 output power db 246 5 10 25 20 3 15 5 v dd = 3v v p = 3v t a = +85 c t a = +25 c t a = 40 c tpc 2. input sensitivity frequency 0 60 2khz output power db 10 50 70 90 30 40 80 20 2khz 900mhz 1khz 1khz ref level = 14.3dbm v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds averages = 10 93.0dbc/hz 100 tpc 3. phase noise (900 mhz, 200 khz, and 20 khz) frequency offset from 900mhz carrier 100hz 1mhz phase noise dbc/hz 40 50 60 70 80 90 100 110 120 130 10db/div r l = 40dbc/hz rms noise = 0.36 140 tpc 4. integrated phase noise (900 mhz, 200 khz, and 20 khz) frequency 0 60 400khz output power db 10 50 70 90 30 40 80 20 400khz 900mhz 200khz 200khz ref level = 14.0dbm v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res bandwidth = 1khz video bandwidth = 1khz sweep = 2.5 seconds averages = 30 91.0dbc/hz 100 tpc 5. reference spurs (900 mhz, 200 khz, and 20 khz) frequency 0 60 2khz output power db 10 50 70 90 30 40 80 20 2khz 5800mhz 1khz 1khz ref level = 10dbm v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 1mhz loop bandwidth = 100khz res bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds averages = 10 84.0dbc/hz 100 tpc 6. phase noise (5.8 ghz, 1 mhz, and 100 khz)
rev. 0 C7C adf4106 frequency offset from 5800mhz carrier 100hz 1mhz phase noise dbc/hz 40 50 140 60 70 80 90 100 110 120 130 10db/div r l = 40dbc/hz rms noise = 1.8 tpc 7. integrated phase noise (5.8 ghz, 1 mhz, and 100 khz) 0 60 100 2mhz output power db 1mhz 5800mhz 1mhz 2mhz 10 50 70 90 30 40 80 20 v dd = 3v, v p = 5v i cp = 5ma pdf frequency = 1mhz loop bandwidth = 100khz res bandwidth = 1khz video bandwidth = 1khz sweep = 13 seconds averages = 1 ref level = 10.0dbm 65.0dbc frequency 66.0dbc tpc 8. reference spurs (5.8 ghz, 1 mhz, and 100 khz) temperature c 60 70 100 40 100 20 phase noise dbc/hz 020406080 80 90 v dd = 3v v p = 5v tpc 9. phase noise (5.8 ghz, 1 mhz, and 100 khz) vs. temperature tuning voltage v 5 15 105 05 1234 45 75 85 95 25 35 65 55 first reference spur dbc v dd = 3v v p = 5v ',-&
.
'9! 0*673& 23 &435 phase detector frequency hz 120 130 180 10 100k 100 output power dbc/hz 1k 10k 140 150 160 170 v dd = 3v v p = 5v ',-&& ,! 0

-, 5 ,%%
: prescaler value 10 9 0 8/9 64/65 16/17 ai dd ma 32/33 4 3 2 1 6 5 8 7 ',-&# ,

rev. 0 adf4106 C8C prescaler output frequency 3.5 3.0 0 50 300 100 di dd ma 150 200 250 2.0 1.5 1.0 0.5 2.5 v dd = 3v v p = 3v tpc 13. di dd vs. prescaler output frequency v cp v 6 0 6 0 5.0 0.5 i cp ma 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 4 2 2 4 v p = 5v i cp = 5ma tpc 14. charge pump output characteristics circuit description reference input section the reference input stage is shown in figure 2. sw1 and sw2 are normally-closed switches. sw3 is normally-open. when powerdown is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power-down. power-down control 100k nc ref in nc no sw1 sw2 sw3 buffer to r counter nc = no connect figure 2. reference input stage rf input stage the rf input stage is shown in figure 3. it is followed by a 2-stage limiting amplifier to generate the cml clock levels needed for the prescaler. av dd 500 1.6v rf in a rf in b 500 agnd bias generator figure 3. rf input stage prescaler (p/p + 1) the dual modulus prescaler (p/p + 1), along with the a and b counters, enables the large division ratio, n, to be realized (n = bp + a). the dual-modulus prescaler, operating at cml levels, takes the clock from the rf input stage and divides it down to a manageable frequency for the cmos a and b counters. the prescaler is programmable. it can be set in soft- ware to 8/9, 16/17, 32/33 or 64/65. it is based on a synchronous 4/5 core. there is a minimum divide ratio possible for fully contiguous output frequencies. this minimum is determined by p, the prescaler value and is given by: (p 2 C p). a and b counters the a and b cmos counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the pll feed- back counter. the counters are specified to work when the prescaler output is 300 mhz or less. thus, with an rf input frequency of 4.0 ghz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid. pulse swallow function the a and b counters, in conjunction with the dual modulus prescaler make it possible to generate output frequencies which are spaced only by the reference frequency divided by r. the equation for the vco frequency is as follows: fpba f r vco refin =+ [( ) ] f vco output frequency of external voltage controlled oscillator (vco). p preset modulus of dual modulus prescaler (8/9, 16/17, etc.,). b preset divide ratio of binary 13-bit counter (3 to 8191). a preset divide ratio of binary 6-bit swallow counter (0 to 63). f refin external reference frequency oscillator.
rev. 0 adf4106 C9C prescaler p/p + 1 13-bit b counter load load n = bp + a from rf input stage to pfd modulus control n divider 6-bit a counter figure 4. a and b counters r counter the 14-bit r counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (pfd). division ratios from 1 to 16,383 are allowed. phase frequency detector (pfd) and charge pump the pfd takes inputs from the r counter and n counter (n = bp + a) and produces an output proportional to the phase and frequency difference between them. figure 5 is a simplified schematic. the pfd includes a programmable delay element which controls the width of the anti-backlash pulse. this pulse ensures that there is no deadzone in the pfd transfer function and minimizes phase noise and reference spurs. two bits in the reference counter latch, abp2 and abp1 control the width of the pulse. see table iii. hi hi d1 d2 q1 q2 clr1 clr2 cp u1 u2 up down charge pump abp2 abp1 cpgnd v p r divider n divider r divider n divider cp output programmable delay u3 figure 5. pfd simplified schematic and timing (in lock) muxout and lock detect the output multiplexer on the adf4110 family allows the user to access various internal points on the chip. the state of muxout is controlled by m3, m2, and m1 in the function latch. table v shows the full truth table. figure 6 shows the muxout section in block diagram form. lock detect muxout can be programmed for two types of lock detect: digital lock detect and analog lock detect. digital lock detect is active high. when ldp in the r counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector cycles is less than 15 ns. with ldp set to 1, five consecutive cycles of less than 15 ns are required to set the lock detect. it will stay set high until a phase error of greater than 25 ns is detected on any sub- sequent pd cycle. the n-channel open-drain analog lock detect should be oper- ated with an external pull-up resistor of 10 k nominal. when lock has been detected this output will be high with narrow low- going pulses. analog lock detect muxout control digital lock detect r counter output n counter output sdout mux dv dd dgnd figure 6. muxout circuit input shift register the adf4110 family digital section includes a 24-bit input shift register, a 14-bit r counter and a 19-bit n counter, com prising a 6-bit a counter and a 13-bit b counter. data is clocked into the 24-bit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of four latches on the rising edge of le. the destina- tion latch is determined by the state of the two con trol bits (c2, c1) in the shift register. these are the two lsbs, db1 and db0, as shown in the timing diagram of figure 1. the truth table for these bits is shown in table vi. table i shows a summary of how the latches are programmed. table i. c2, c1 truth table control bits c2 c1 data latch 0 0 r counter 0 1 n counter (a and b) 1 0 function latch (including prescaler) 1 1 initialization latch
rev. 0 adf4106 C10C table ii. latch summary db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 abp1 abp2 t1 t2 ldp control bits 14-bit reference counter test mode bits db21 db22 db23 00 anti- backlash width reference counter latch n counter latch x db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 a6 control bits 6-bit a counter 13-bit b counter db21 reserved db22 db23 cp gain g1 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) f1 pd1 m1 m2 m3 f3 p1 p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 control bits counter reset power- down 1 muxout control pd polarity power- down 2 current setting 1 prescaler value timer counter control cpi3 cpi4 db21 current setting 2 tc3 tc2 tc1 db22 db23 fastlock enable fastlock mode f4 f5 function latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (1) f1 pd1 m1 m2 m3 f3 p1 p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 control bits counter reset power- down 1 muxout control pd polarity power- down 2 current setting 1 prescaler value timer counter control cpi3 cpi4 db21 current setting 2 tc3 tc2 tc1 db22 db23 fastlock enable fastlock mode f4 f5 initialization latch lock detect precision cp three- state cp three- state reserved
rev. 0 adf4106 C11C table iii. reference counter latch map ldp operation 0 three consecutive cycles of phase delay less than 15ns must occur before lock detect is set. 1 five consecutive cycles of phase delay less than 15ns must occur before lock detect is set. test mode bits should be set to 00 for normal operation abp2 abp1 antibacklash pulsewidth 0 0 2.9ns 0 1 1.3ns 1 0 6.0ns 1 1 2.9ns r14 r13 r12 .......... r3 r2 r1 divide ratio 0 0 0 .......... 0011 0 0 0 .......... 0102 0 0 0 .......... 0113 0 0 0 .......... 1004 . . . .......... .... . . . .......... .... . . . .......... .... 1 1 1 .......... 1 0 0 16380 1 1 1 .......... 1 0 1 16381 1 1 1 .......... 1 1 0 16382 1 1 1 .......... 1 1 1 16383 x = don t care both of these bits must be set to 0 for normal operation db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 abp1 abp2 t1 t2 ldp control bits 14-bit reference counter test mode bits db21 db22 db23 0 0 anti- backlash width x lock detect precision reserved
rev. 0 adf4106 C12C table iv. ab counter latch map db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 a6 control bits 6-bit a counter 13-bit b counter db21 reserved db22 db23 cp gain g1 these bits are not used by the device and are don't care bits. f4 (function latch) fastlock enable cp gain operation 0 0 charge pump current setting 1 is permanently used 0 1 charge pump current setting 2 is permanently used 1 0 charge pump current setting 1 is used 1 1 charge pump current is switched to setting 2. the time spent in setting 2 is dependent on which fastlock mode is used. see function latch description a counter a6 a5 .......... a2 a1 divide ratio 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 60 1 1 .......... 0 1 61 1 1 .......... 1 0 62 1 1 .......... 1 1 63 n = bp + a, p is prescaler value set in the function latch. b must be greater than or equal to a. for continuously adjacent values of (n f ref ), at the output, n min is (p 2 - p) xx x = don t care b13 b12 b11 b3 b2 b1 b counter divide ratio 0 0 0 .......... 0 0 0 not allowed 0 0 0 .......... 0 0 1 not allowed 0 0 0 .......... 0 1 0 not allowed 0 0 0 .......... 1 1 1 3 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 8188 1 1 1 .......... 1 0 1 8189 1 1 1 .......... 1 1 0 8190 1 1 1 .......... 1 1 1 8191
rev. 0 adf4106 C13C table v. function latch map p2 p1 prescaler value 0 0 8/9 0 1 16/17 1 0 32/33 1 1 64/65 ce pin pd2 pd1 mode 0 x x asynchronous power-down 1 x 0 normal operation 101asy nchronous power-down 111sy nchronous power-down cpi6 cpi5 cp14 i cp (ma) cpi3 cpi2 cpi1 3k 5.1k 11k 0 0 0 1.06 0.625 0.289 0 0 1 2.12 1.25 0.580 0 1 0 3.18 1.875 0.870 0 1 1 4.24 2.5 1.160 1 0 0 5.30 3.125 1.450 1 0 1 6.36 3.75 1.730 1 1 0 7.42 4.375 2.020 1 1 1 8.50 5.0 2.320 timeout tc4 tc3 tc2 tc1 (pfd cycles) 00003 00017 001011 001115 010019 010123 011027 011131 100035 100139 101043 101147 110051 110155 111059 111163 f4 0 1 1 m3 m2 m1 000 001 010 011 dv dd 100 101 110 111 f3 0 1 f2 0 1 f1 0 1 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) f1 pd1 m1 m2 m3 f3 p1 p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 control bits counter reset power- down 1 muxout control pd polarity cp three- state power- down 2 current setting 1 prescaler value timer counter control cpi3 cpi4 db21 current setting 2 tc3 tc2 tc1 db22 db23 fastlock enable fastlock mode f4 f5 charge pump output normal three-state fastlock mode fastlock disabled fastlock mode 1 fastlock mode 2 counter operation normal r, a, b counters held in reset f5 x 0 1 output three-state output digital lock detect (active high) n divider output dv dd r divider output n-channel open-drain lock detect serial data output dgnd phase detector polarity negative positive
rev. 0 adf4106 C14C table vi. initialization latch map p2 p1 prescaler value 0 0 8/9 0 1 16/17 1 0 32/33 1 1 64/65 ce pin pd2 pd1 mode 0 x x asynchronous power-down 1 x 0 normal operation 101asy nchronous power-down 111sy nchronous power-down cpi6 cpi5 cp14 i cp (ma) cpi3 cpi2 cpi1 3k 5.1k 11k 0 0 0 1.06 0.625 0.289 0 0 1 2.12 1.25 0.580 0 1 0 3.18 1.875 0.870 0 1 1 4.24 2.5 1.160 1 0 0 5.30 3.125 1.450 1 0 1 6.36 3.75 1.730 1 1 0 7.42 4.375 2.020 1 1 1 8.50 5.0 2.320 timeout tc4 tc3 tc2 tc1 (pfd cycles) 00003 00017 001011 001115 010019 010123 011027 011131 100035 100139 101043 101147 110051 110155 111059 111163 f4 0 1 1 m3 m2 m1 000 001 010 011 dv dd 100 101 110 111 f3 0 1 f2 0 1 f1 0 1 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (1) f1 pd1 m1 m2 m3 f3 p1 p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 control bits counter reset power- down 1 muxout control pd polarity cp three- state power- down 2 current setting 1 prescaler value timer counter control cpi3 cpi4 db21 current setting 2 tc3 tc2 tc1 db22 db23 fastlock enable fastlock mode f4 f5 charge pump output normal three-state fastlock mode fastlock disabled fastlock mode 1 fastlock mode 2 counter operation normal r, a, b counters held in reset f5 x 0 1 output three-state output digital lock detect (active high) n divider output dv dd r divider output n-channel open-drain lock detect serial data output dgnd phase detector polarity negative positive
rev. 0 adf4106 C15C fastlock mode 2 the charge pump current is switched to the contents of current setting 2. the device enters fastlock by having a 1 written to the cp gain bit in the ab counter latch. the device exits fastlock under the control of the timer counter. after the timeout period determined by the value in tc4 C tc1, the cp gain bit in the ab counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. see table v for the timeout periods. timer counter control the user has the option of programming two charge pump cur- rents. the intent is that the current setting 1 is used when the rf output is stable and the system is in a static state. current setting 2 is meant to be used when the system is dynamic and in a state of change (i.e., when a new output frequency is programmed). the normal sequence of events is as follows: users initially decide what the preferred charge pump currents are will be. for example, they may choose 2.5 ma as current setting 1 and 5 ma as the current setting 2. at the same time they must also decide how long they want the secondary cur- rent to stay active before reverting to the primary current. this is controlled by the timer counter control bits db14 to db11 (tc4 C tc1) in the function latch. the truth table is given in table v. now, when users wish to program a new output frequency, they can simply program the ab counter latch with new values for a and b. at the same time they can set the cp gain bit to a 1, which sets the charge pump with the value in cpi6 C cpi4 for a period of time determined by tc4 C tc1. when this time is up, the charge pump current reverts to the value set by cpi3 C cpi1. at the same time the cp gain bit in the a, b counter latch is reset to 0 and is now ready for the next time that the user wishes to change the frequency again. note that there is an enable feature on the timer counter. it is enabled when fastlock mode 2 is chosen by setting the fastlock mode bit (db10) in the function latch to 1. charge pump currents cpi3, cpi2, cpi1 program current setting 1 for the charge pump. cpi6, cpi5, cpi4 program current setting 2 for the charge pump. the truth table is given in table v. prescaler value p2 and p1 in the function latch set the prescaler values. the prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 300 mhz. thus, with an rf frequency of 4 ghz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid. pd polarity this bit sets the phase detector polarity bit. see table v. cp three-state this bit controls the cp output pin. with the bit set high, the cp output is put into three-state. with the bit set low, the cp output is enabled. the function latch with c2, c1 set to 1,0, the on-chip function latch will be programmed. table v shows the input data format for program- ming the function latch. counter reset db2 (f1) is the counter reset bit. when this is 1, the r counter and the a,b counters are reset. for normal operation this bit should be 0. upon powering up, the f1 bit needs to be disabled (set to ??. the n counter then resumes counting in ?lose?align- ment with the r counter. (the maximum error is one prescaler cycle) . power-down db3 (pd1) and db21 (pd2) on the adf4110 family, provide programmable power-down modes. they are enabled by the ce pin. when the ce pin is low, the device is immediately disabled regardless of the states of pd2, pd1. in the programmed asyn- chronous power-down, the device powers down immediately after latching a 1 into bit pd1, with the condition that pd2 has been loaded with a 0. in the programmed synchronous power-down, the device power down is gated by the charge pump to prevent unwanted frequency jumps. once the power- down is enabled by writing a 1 into bit pd1 (on condition that a 1 has also been loaded to pd2), then the device will go into power-down on the occurrence of the next charge pump event. when a power down is activated (either synchronous or asynchronous mode including ce-pin-activated power down), the following events occur: all active dc current paths are removed. the r, n, and timeout counters are forced to their load state conditions. the charge pump is forced into three-state mode. the digital clock detect circuitry is reset. the rf in input is debiased. the reference input buffer circuitry is disabled. the input register remains active and capable of loading and latching data. muxout control the on-chip multiplexer is controlled by m3, m2, m1 on the adf4110 family. table v shows the truth table. fastlock enable bit db9 of the function latch is the fastlock enable bit. only when this is 1 is fastlock enabled. fastlock mode bit db10 of the function latch is the fastlock mode bit. when fastlock is enabled, this bit determines which fastlock mode is used. if the fastlock mode bit is 0, fastlock mode 1 is selected and if the fastlock mode bit is 1, fastlock mode 2 is selected. fastlock mode 1 the charge pump current is switched to the contents of current setting 2. the device enters fastlock by having a 1 written to the cp gain bit in the ab counter latch. the device exits fastlock by having a 0 written to the cp gain bit in the ab counter latch.
rev. 0 adf4106 C16C the initialization latch when c2, c1 = 1, 1, the initialization latch is programmed. this is essentially the same as the function latch (programmed when c2, c1 = 1, 0). however, when the initialization latch is programmed there is an additional internal reset pulse applied to the r and ab counters. this pulse ensures that the ab counter is at load point when the ab counter data is latched and the device will begin counting in close phase alignment. if the latch is programmed for synchronous power-down (ce pin is high; pd1 bit is high; pd2 bit is low), the internal pulse also triggers this powerdown. the prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse and so close phase alignment is maintained when counting resumes. when the first ab counter data is latched after initialization, the internal reset pulse is again activated. however, successive ab counter loads after this will not trigger the internal reset pulse. device programming after initial power-up after initially powering up the device, there are three ways to program the device. initialization latch method ? apply v dd . ? program the initialization latch ( 11 in two lsbs of input word). make sure that f1 bit is programmed to 0. ? do a function latch load ( 10 in two lsbs of the control word), making sure that the f1 bit is programmed to a 0. ? do an r load ( 00 in two lsbs). ? do an ab load ( 01 in two lsbs). when the initialization latch is loaded, the following occurs: 1. the function latch contents are loaded. 2. an internal pulse resets the r, a, b and timeout counters to load state conditions and also three-states the charge pump. note that the prescaler bandgap reference and the oscillator input buffer are unaffected by the internal reset pulse, allow- ing close phase alignment when counting resumes. 3. latching the first ab counter data after the initialization word will activate the same internal reset pulse. successive ab loads will not trigger the internal reset pulse unless there is another initialization. ce pin method ? apply v dd . ? bring ce low to put the device into power-down. this is an asynchronous power-down in that it happens immediately. ? program the function latch (10). ? program the r counter latch (00). ? program the ab counter latch (01). ? bring ce high to take the device out of power-down. the r and ab counters will now resume counting in close alignment. note that after ce goes high, a duration of 1 s may be required for the prescaler bandgap voltage and oscillator input buffer bias to reach steady state. ce can be used to power the device up and down in order to check for channel activity. the input register does not need to be reprogrammed each time the device is disabled and enabled as long as it has been programmed at least once after v dd was initially applied. counter reset method ? apply v dd . ? do a function latch load ( 10 in two lsbs). as part of this, load 1 to the f1 bit. this enables the counter reset. ? do an r counter load ( 00 in two lsbs). ? do an ab counter load ( 01 in two lsbs). ? do a function latch load ( 10 in two lsbs). as part of this, load 0 to the f1 bit. this disables the counter reset. this sequence provides the same close alignment as the initial- ization method. it offers direct control over the internal reset. note that counter reset holds the counters at load point and three-states the charge pump, but does not trigger synchronous power-down. application section local oscillator for lmds base station transmitter figure 7 shows the adf4106 being used with a vco to pro- duce the lo for an lmds base station operation in the 5.4 ghz to 5.8 ghz band. the reference input signal is applied to the circuit at fref in and, in this case, is terminated in 50 ? . a typical base station system would have either a tcxo or an ocxo driving the reference input without any 50 ? termination. in order to have a channel spacing of 1 mhz at the output, the 10 mhz reference input must be divided by 10, using the on-chip reference divider of the adf4106. the charge pump output of the adf4106 (pin 2) drives the loop filter. in calculating the loop filter component values, a number of items need to be considered. in this example, the loop filter was designed so that the overall phase margin for the system would be 45 degrees. other pll system specifications are given below: k d = 2.5 ma k v = 80 mhz/v loop bandwidth = 50 khz f ref = 1 mhz n = 5800 extra reference spur attenuation = 10 db all of these specifications are needed and used to come up with the loop filter component values shown in figure 7. figure 7 gives a typical phase noise performance of C 83 dbc/hz at 1 khz offset from the carrier. spurs are better than C 62 dbc. the loop filter output drives the vco, which, in turn, is fed back to the rf input of the pll synthesizer and also drives the rf output terminal. a t-circuit configuration provides 50 ? matching between the vco output, the rf output and the rf in terminal of the synthesizer. note that the adf4106 rf input looks like 50 ? at 5.8 ghz and so no terminating resistor is needed. when operating at lower frequencies however, this is not the case. in a pll system, it is important to know when the system is in lock. in figure 7, this is accomplished by using the muxout signal from the synthesizer. the muxout pin can be pro- grammed to monitor various internal signals in the synthesizer. one of these is the ld or lock-detect signal.
rev. 0 adf4106 C17C adf4106 v940me03 fref in rf out v dd v p v cc ce clk data le spi compatible serial bus 1000pf 1000pf refin note decoupling capacitors (0.1 f/10pf) on av dd , dv dd , v p of the adf4106 and on v cc of the v940me03 have been omitted from the diagram to aid clarity. 100pf av dd dv dd v p cp muxout lock detect rf in a rf in b cpgnd agnd dgnd 100pf 1.5nf 20pf 100pf 100pf 1, 3, 4, 5, 7, 8, 9, 11, 12, 13 r set 5.1k 51 6.2k 4.3k 100pf 18 18 18 figure 7. local oscillator for lmds base station interfacing the adf4106 has a simple spi-compatible serial interface for writing to the device. sclk, sdata and le control the data transfer. when le (latch enable) goes high, the 24 bits which have been clocked into the input register on each rising edge of sclk will get transferred to the appropriate latch. see figure 1 for the timing diagram and table i for the latch truth table. the maximum allowable serial clock rate is 20 mhz. this means that the maximum update rate possible for the device is 833 khz or one update every 1.2 s. this is certainly more than adequate for systems which will have typical lock times in hundreds of microseconds. aduc812 interface figure 8 shows the interface between the adf4106 and the aduc812 microconverter. since the aduc812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. the microconverter is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the adf4106 needs a 24-bit word. this is accomplished by writing three 8-bit bytes from the microconverter to the device. when the third byte has been written the le input should be brought high to complete the transfer.
rev. 0 adf4106 C18C on first applying power to the adf4106, it needs at three writes (one each to the r counter latch, the n counter latch and the function latch) for the output to become active. i/o port lines on the aduc812 are also used to control power-down (ce input) and to detect lock (muxout config- ured as lock detect and polled by the port input). when operating in the mode described, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maximum rate at which the output frequency can be changed will be 166 khz. aduc812 adf4106 sclk sdata le ce muxout (lock detect) sclock mosi i/o ports figure 8. aduc812 to adf4106 interface adsp-2181 interface figure 9 shows the interface between the adf4106 and the adsp-21xx digital signal processor. the adf4106 needs a 24-bit serial word for each latch write. the easiest way to accomplish this using the adsp-21xx family is to use the autobuffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. set up the word length for 8 bits and use three memory locations for each 24-bit word. to program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode and then write to the transmit register of the dsp. this last operation initiates the autobuffer transfer. adsp-21xx adf4106 sclk sdata le ce muxout (lock detect) sclock mosi i/o flags tfs figure 9. adsp-21xx to adf4106 interface
rev. 0 adf4106 C19C outline dimensions dimensions shown in inches and (mm). 16-lead thin shrink so package (tssop) (ru-16) 16 9 8 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.201 (5.10) 0.193 (4.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 20-leadless frame chip scale package (lfcsp) (cp-20) 1 20 5 6 11 16 15 bottom view 10 0.080 (2.25) 0.083 (2.10) sq 0.077 (1.95) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.030 (0.75) 0.022 (0.60) 0.014 (0.50) 0.012 (0.30) 0.009 (0.23) 0.007 (0.18) 0.080 (2.00) ref 0.010 (0.25) min 0.020 (0.50) bsc 12 max 0.008 (0.20) ref 0.031 (0.80) max 0.026 (0.65) nom 0.002 (0.05) 0.0004 (0.01) 0.0 (0.0) 0.035 (0.90) max 0.033 (0.85) nom seating plane controlling dimensions are in millimeters pin 1 indicator top view 0.148 (3.75) bsc sq 0.157 (4.0) bsc sq
C20C c02720C.8C10/01(0) printed in u.s.a.

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